A conventional computing platform comprises a printed circuit board (PCB), commonly referred to as a motherboard, including a processor and one or more additional chips (e.g., memory controllers, video graphic adapters, etc.) that together form a processing core for the computing platform. Among other things, the designer and/or manufacturer of the PCB designs and/or configures how hardware error events are handled by the computing platform. For instance, the designer and/or manufacturer may connect hardware error indicating output signals from the one or more additional chips to interrupt inputs for the processor, thereby making the processor aware when a hardware error has occurred on the motherboard. Further, the designer and/or manufacturer may provide firmware and/or configure an operating system executing on the processor to control how hardware error events are processed. While a first example manufacturer relies on the operating system to own and handle all hardware error events and hardware error information, another manufacturer relies on the firmware to handle all hardware error events and to configure the firmware to hide hardware resources from the operating system. Further, the two example manufacturers may utilize different types of external processor interrupts (e.g., system management interrupt (SMI), non-maskable interrupt (NMI), etc.) to indicate hardware error events to the processor.
Increasingly, semiconductor device designers and/or manufacturers are implementing more of the functionality provided by the one or more additional chips inside the semiconductor package of the processor. Further, the semiconductor package may include multiple processor cores. However, such conventional system-on-a-chip devices eliminate the current flexibility that the designer and/or manufacturer of a computing platform have to control how and/or where error event handling is performed. In particular, the computing platform designer and/or manufacturer no longer has access to hardware error control signals provided by the functional blocks implementing the functionality previously provided by the one or more additional chips and, thus, is unable to route, via the PCB, the hardware error signals to desired destinations (e.g., processor interrupts). Instead, the semiconductor device designer and/or manufacturer controls and/or determines the routing of the hardware error control signals.